FPGA
The Altera 10K30A FPGA is the heart of the logic analyzer. An FPGA (Field Programmable Gate Array) is a chip containing a large number of general-purpose logic elements with an interconnection matrix. The logic elements and the interconnections are configured by downloading a data file into the device, either from an EPROM or from the parallel port of a PC. The functionality of the device is determined entirely by the downloaded code. The code which I created for this project implements a logic analyzer, but an entirely different instrument could be created simply by modifying the configuration file.
The configuration file is created by a logic compiler. Altera provides a compiler as part of their "Max+PlusII" software for Windows. This software provides a complete design environment, from design entry through synthesis, simulation, and programming the FPGA. The logic design can be created as a schematic or by using a hardware description language such as VHDL, or by a combination of both methods. I chose to use schematic entry, since it provides a more direct representation of the logic which will be created in the device. Max+PlusII encourages a hierarchical approach to design, allowing you to create logic modules which can be incorporated into higher-level modules and eventually into the top-level module which is the complete design. Either "top-down" or "bottom-up" approaches can be used. The simulator is invaluable for debugging, and can be used with individual modules or the complete design.
Max+PlusII can be downloaded from the Altera web-site, using the link below. It is free, but you have to register and then Altera will email you a license file. The current free version is 10.0. I used the commercial version 9.5 for this project. The main advantage of the commercial version is that it supports "timing-driven synthesis", which can result in higher speed. Using the commercial version of the software, the logic analyzer runs at 112 MHz (in simulation) vs. about 87 MHz using the free version.
The top-level schematic page for my logic analyzer FPGA is shown below. It uses high-level modules such as "ISA_INTERFACE" which have their own schematic pages, incorporating lower level modules which have their own pages, etc., etc. If you want to peruse the complete design, you can download the design files (using the links below) and look at them in Max+PlusII.
Click here for medium-sized image (48 KB)
Click here for larger image (165 KB)
Click here to download logic analyzer design files (PC/104 Version)
Click here to download logic analyzer design files (parallel port version)
Click here for Altera download page