FPGA-based Logic Analyzer
Version 1.00
Help File
Table of Contents
- Download the software from eebit.com as a ZIP archive. The file will be called something like logic_1_0_0_bin.zip (for version 1.00)
- Unzip the file into a folder such as C:\logic. This will be
your working directory.
- After unzipping, you should have the following files and folder in your working directory:
- logic2.exe - the executable
- logic_pp.rbf - configuration file for the FPGA
- instdrv.exe - utility for installing NT drivers
- giveio.sys - NT port driver
- default.las - setup file
- default.lad - data file
- doc - folder containing documentation, including this help file
- Note that instdrv.exe and giveio.sys are only necessary for
Windows NT, 2000, or XP. They will be called automatically
from logic2.exe.
- The files default.las and default.lad are not really necessary, but it is a good idea to
keep at least one *.las and *.lad file in the folder because otherwise
when you save a setup or data file, the File Save dialog in Windows will
default to your My Documents folder, instead of your working
directory.
- Double-click on logic2.exe to start the application.
- Download the source files from eebit.com as a ZIP archive. The file will be called something like logic_1_0_0_source.zip (for version 1.00)
- Unzip the file into a folder such as C:\logic_source.
- After unzipping, your folder should contain a file called v.dsw and the following subdirectories:
- logic2 - source files for the logic2.exe application
- include/v - header files for the V library
- vlib - source files for the V library (version 1.25)
- bin - binaries
- bin/doc - documentation, including this help file
- If you are using Microsoft Visual C++, you can double-click on v.dsw to open a workspace. This workspace contains 2 projects:
- logic2 - this is the project for the logic analyzer application
- vlib - this is the project for the V library, compiled as a static library
- Now you should be able to compile and run logic2.exe.
- If you are using a compiler other than MSVC++, you will have to create your own makefile, which should be pretty simple. If you have trouble getting vlib to compile, please refer to the objectcentral.com website.
- Prior to running logic2.exe for the first time, determine the hardware
address of the parallel port on your PC. This will probably be 0x378.
- For the logic analyzer to work, the parallel port must be in bidirectional mode. All modern PCs have bidirectional parallel ports, but the port may be configured through the BIOS setup to be unidirectional. This is sometimes referred to as "compatibility mode". Check your BIOS settings, and if necessary change the port to PS/2, EPP or ECP mode.
- Attach a cable from the parallel port to the logic analyzer.
- Power up the analyzer. Connect one of the inputs to a signal source, if available.
- Launch logic2.exe.
- Click on the Connect button on the taskbar to open the Connect
dialog. The default setting for the parallel port address is 0x378.
If this is not correct for your system, change it and then click
on Save Settings. Then click on OK to connect to the logic analyzer
and download the FPGA code. If all is well, a dialog will appear
after a few seconds indicating successful completion of the download.
If unsuccessful, the dialog should give an error message describing
the problem.
- Now you can run the analyzer by clicking on the Run button on the
taskbar. With the default settings, it will trigger immediately and
a dialog will appear telling you how much data was accumulated. When
you dismiss this dialog, the data buffer will upload and be displayed.
- If you have gotten this far, the analyzer should be working properly.
The logic2.exe application allows you to connect to the analyzer, run it, and examine the data that it collects. The user interface is fairly simple, consisting of:
- File menu
- Open Setup - open setup file
- Open Data - open data file
- Save Setup as... - save setup file, default extension is .las
- Save Data as... - save data file, default extension is .lad
- Test Data - fill buffer with dummy data
- Exit
- Taskbar
- Connect - connect to analyzer
- Run - start capturing data, wait for trigger
- Stop - stop capture
- Clock - select clock
- Cycles post-Trigger - set number of cycles to capture post-trigger
- << - scroll data window left 5 divisions
- < - scroll data window left 1 division
- > - scroll data window right 1 division
- >> - scroll data window right 5 divisions
- + - zoom in on data X 2
- - - zoom out on data X 2
- T - center data window on trigger
- C - center data window on cursor
- R - reset data window to defaults
- Data - show data window
- Setup - show setup window
- Trigger - show trigger window
- Main window - this can be switched to 3 views, using taskbar buttons
- Data - shows data as waveforms and hex
- Setup - assign symbols to inputs
- Trigger - set trigger condition
- Status bar
- Time/date
- Connection type - not connected, parallel port or IP address
- Clock setting
- Connection status
This window displays data from the logic analyzer as waveforms (for single-bit signals) and hex numbers (for bussed signals).
Selecting Test Data from the File menu loads some dummy data, so that you can experiment with the user interface without actually running the analyzer. This will produce the display shown below:
Signal names are assigned to combinations of input pins using the Setup window (see below), and these names are displayed along the left edge of the Data window. The order of the signal names can be changed by dragging them up or down with the left mouse button. Signal names can be edited or deleted by right-clicking them.
The main part of the Data window is used to display the data for each signal. This part of the window can be scrolled left or right and zoomed in or out using taskbar buttons. A horizontal scale is shown along the top of the waveform display indicating the position of the data points relative to the trigger point. The trigger point is represented by a vertical red line with "T" at its upper end.
A cursor can be applied to the data by left-clicking the mouse at the appropriate data point. This will be displayed as a violet-colored vertical line with "C" at its upper end. The VALUE column next to the list of signal names shows the value of each signal at the cursor.
A second marker can be applied by right-clicking the mouse. This will be displayed as a vertical blue line with "M" at its upper end. The positions of the cursor and the marker are displayed numerically at the top of the window, along with the distance between them.
Clicking the T button on the taskbar centers the window on the trigger point, while clicking the C or M buttons centers the window on the cursor or marker, respectively.
This window is used to assign signal names to combinations of input pins.
The signal names are shown at the left side of the window, next to a grid with the pin numbers along the top. One or more pins can be assigned to each signal name, by clicking on the appropriate squares of the grid. When a pin is assigned, an "*" is placed in the grid square. Clicking the square again de-assigns the pin. Pins can be assigned to multiple names, if desired. Signal names with no assigned pins are indicated by a grey background.
The order of the signal names in the list can be changed by dragging them up or down with the left mouse button. Names can be edited or deleted by right clicking them. Up to 32 names are allowed. If there are fewer then 32 names assigned, there will be an entry at the bottom of the name list called "Add new name". Clicking on this will allow adding a new name to the list.
This window is used to set the trigger condition for the analyzer. The trigger condition can be represented as:
STATE1 for N cycles followed by STATE2
STATE1 is a combination of 0, 1 or "don't care" on each pin. STATE2 is a combination of 0, 1, "rising edge", "falling edge", "any edge" or "don't care" on each pin. N is an integer from 0 to 255. Setting N to zero effectively disables the STATE1 detector (which is the same as setting each pin in STATE1 to "don't care".)
The condition assigned to each pin is shown on a grid next to the signal names. The violet part of the grid is for STATE1, and the blue part of the grid is for STATE2. To set the condition of each pin for either state, click on the appropriate square of the grid. Each click will scroll the setting for the pin through the sequence of available states.
The value of N is displayed in the caption above the STATE1 grid, within a light blue rectangle. Clicking on this rectangle pops up a dialog which allows editing the value.
In the screenshot shown above, the analyzer will trigger when BUS[16:9] = D6 for 5 cycles, followed by a falling edge on PIN_1.
Click on the Connect button on the taskbar. A dialog will open, with fields for:
- Choosing the parallel port or network interface
- Setting the parallel port address (in hex) (default = 378)
- Selecting the filename for the FPGA configuration file (default = logic_pp.rbf)
- Selecting the filename for the port driver for NT (default = giveio.sys)
- Setting the IP address for the networked version of the analyzer
Assuming that you are using the parallel port version, check that the port address is correct, and change it if necessary. If you have to change it, click on Save Settings to save your change. Then click on OK. After a few seconds, a dialog should appear confirming a successful download. If an error occurs, the dialog will give an error message to help you troubleshoot the problem.
Before running the analyzer, check the settings for the Clock and the Cycles post-Trigger in the taskbar. Then click on the Run button. The analyzer will capture data for about 1/2 second in order to fill the data buffer. It then continues capturing while waiting for the trigger condition to be met. When it detects the trigger, it captures the number of post-trigger cycles which were requested, and then stops. If no trigger is detected, it will keep running until you click Stop. When the analyzer stops, a dialog will pop up indicating the number of cycles captured and the start and trigger positions in the SRAM buffer.
When you dismiss the dialog, the data will be uploaded into the data buffer, which is 64000 cycles long. The number of pre-trigger cycles will be equal to 64000 minus the number of post-trigger cycles. For example, if you requested 16000 cycles post-trigger, there will be 48000 cycles pre-trigger. If you can't see the trigger point in the Data window, click on T in the taskbar.
From the File menu:
- select Save Setup as... to save setup information (ie. signal names, pin assignments, trigger settings and acquisition parameters) to a file. The default file extension is .las.
- select Open Setup to load a setup file, or load the setup parameters from a data file.
- select Save Data as... to save the data buffer to a file. Setup information is saved as well. The default extension is .lad.
- select Open Data to load a data file.
- select Test Data to load dummy data.
last revised Dec-21-2001 by Allan Wright